The present invention relates to semiconductor devices, and more particularly to a metal oxide semiconductor field effect transistor (MOSFET) which comprises a patterned gate stack region that includes a metallic gate electrode formed atop a polysilicon gate electrode, wherein sidewall spacers are present on a portion of the patterned gate stack region such that the metallic gate electrode is protected from being oxidized during a subsequent sidewall oxidation process. The present invention also relates to a method of fabricating the inventive MOSFET.
Modern Si-based metal-insulator-semiconductor (MIS) field effect transistors (FETs) are fabricated with the use of so-called sidewall or corner oxidation of the gate corner. Sidewall oxidation processes are routinely employed in conventional process flows such as complementary metal oxide semiconductor (CMOS) logic, static random access memory (SRAM), dynamic random access memory (DRAM), embedded DRAM, flash memories and other like processing flows.
As is known to those skilled in the art, sidewall oxidation of the gate corners thickens the gate insulator, e.g., gate dielectric, at the gate corner. Thick corner insulators prevent electrical breakdown at the device corners. The corner insulator also reduces the electric field by effectively rounding the corner during oxidation. A higher gate corner electric field can produce gate induced drain leakage (GIDL) and large hot-carrier effects leading to poor transistor reliability. In addition, the planar oxide grown during corner oxidation is used as a screen oxide for a subsequent ion-implantation step, thus, simplifying process integration flow. All these benefits of sidewall (or corner) oxidation are well known in the art; therefore a detailed discussion concerning the same is not needed herein.
When the gate region includes a low-resistivity metallic gate electrode, the sidewall oxidation process typically causes degradation of the metallic gate. This degradation is caused by junction diffusion that occurs during the high-temperature sidewall oxidation process. Moreover, during high-temperature sidewall oxidation, portions of the metallic gate are oxidized. Oxidation of the metallic gate electrode is undesirable since it results in an increase in the resistivity of the gate region.
Another problem with conventional FET devices is that the adjoining lightly doped source/drain regions and halo implant regions which are formed into a surface of a semiconductor substrate are subjected to the thermal cycle used in activating the heavily doped source/drain diffusion regions. This occurs because the lightly doped source/drain regions and/or halo implants are typically formed prior to formation of the heavily doped source/drain diffusion regions. It is emphasized that subjecting the lightly doped source/drain regions and/or halo implants to the thermal cycle of activating the heavily doped source/drain diffusion regions is undesirable since the impurity dopants will diffuse and alter the junction depth profile during thermal processing.
In view of the above problems with prior art metallic gate structures, there is a continued need for developing a new and improved MOSFET in which the metallic gate is protected in a manner such that the metallic gate is not degraded during a subsequent sidewall oxidation process.
One object of the present invention is to provide a MOSEFT which includes a metallic gate electrode formed atop a polysilicon gate electrode in which the metallic gate electrode is highly resistant to high-temperature degradation during a subsequent sidewall oxidation process.
Another object of the present invention is to provide a MOSFET with a metallic gate electrode wherein the lightly doped source/drain regions and/or halo implant regions are not affected by activation of heavily doped source/drain diffusion regions.
A yet other object of the present invention is to provide a MOSFET with a metallic gate electrode wherein the MOSFET is formed utilizing processing steps, including typical sidewall oxidation processes, that are compatible with existing CMOS processing steps.
These and other objects and advantages are achieved in the present invention by protecting the metallic gate electrode sidewall with a localized oxidation barrier and by forming the heavily doped source/drain diffusion regions in the substrate prior to forming the lightly doped source/drain regions and/or halo implant regions. The localized oxidation barrier which is formed on at least the sidewalls of the metallic gate electrode is referred herein as a hanging spacer.
One aspect of the present invention thus relates to a method of forming a MOSFET having a metallic gate electrode that is protected from high-temperature degradation. Specifically, the inventive method of the present invention comprises the steps of:
(a) forming a placeholder dielectric on exposed horizontal surfaces of a semiconductor structure, said semiconductor structure comprising at least a semiconductor substrate having a patterned gate dielectric and a patterned gate region formed thereon, wherein said patterned gate region comprises at least a metallic gate electrode formed atop a polysilicon gate electrode;
(b) forming sidewall spacers on exposed sidewalls of said patterned gate region and on a surface of said placeholder dielectric;
(c) removing said placeholder dielectric from said semiconductor structure so as to at least expose a portion of said polysilicon gate electrode of said patterned gate region, but not said metallic gate electrode;
(d) performing a sidewall oxidation process so as to form a thermal oxide layer on at least said exposed portion of said polysilicon gate electrode, but not said metallic gate electrode;
(e) forming heavily doped source/drain diffusion regions in said semiconductor substrate; and
(f) forming lightly doped source/drain regions, halo implant regions or both said lightly doped source/drain regions and halo implant regions in said semiconductor substrate.
Another aspect of the present invention relates to a semiconductor structure which is fabricated utilizing the inventive method recited above. Specifically, the semiconductor structure of the present invention comprises:
a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, said patterned gate region including at least a metallic gate electrode formed atop a polysilicon gate electrode;
sidewall spacers, i.e., hanging spacers, formed on an upper portion of said patterned gate region including at least said metallic gate electrode; and
a thermal oxide layer formed on lower portions of said patterned gate region including a portion of said polysilicon gate electrode, but not said metallic gate electrode.